gm71c(s)17403c/cl 4,194,304 words x 4 bit cmos dynamic ram description the gm71c(s)17403c/cl is the new generation dynamic ram organized 4,194,304 words x 4 bit. gm71c(s)17403c/cl has realized higher density, higher performance and various functions by utilizing advanced cmos process technology. the gm71c(s)17403c/cl offers extended data out (edo) mode as a high speed access mode. multiplexed address inputs permit the gm71c(s)17403c/cl to be packaged in a standard 300 mil 24(26) pin soj and a standard 300mil 24(26) pin plastic tsop ii. the package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. system oriented features include single power supply 5v+/-10% tolerance, direct interfacing capability with high performance logic families such as schottky ttl. features * 4,194,304 words x 4 bit organization * extended data out mode capability * single power supply (5v+/-10%) * fast access time & cycle time * low power active : 660/605/550mw (max) standby : 11mw (cmos level : max) : 0.83 mw (l-version : max) * ras only refresh, cas before ras refresh, hidden refresh capability * all inputs and outputs ttl compatible * 2048 refresh cycles/32ms * 2048 refresh cycles/128ms (l-version) * battery backup operation (l-version) * test function : 16bit parallel test mode ( unit: ns) t rac t cac t rc t hpc gm71c(s)17403c/cl-6 gm71c(s)17403c/cl-7 60 70 15 18 104 124 25 30 gm71c(s)17403c/cl-5 50 13 84 20 pin configuration ( top view) v cc i/o1 i/o2 we ras nc a10 a0 a1 a2 a3 v cc v ss i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 24(26) soj 24(26) tsop ii v cc i/o1 i/o2 we ras a11 a10 a0 a1 a2 a3 v cc v ss i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 rev 0.1 / apr ? 01
gm71c(s)17403c/cl rev 0.1 / apr ? 01 pin description pin function pin function a0-a10 a0-a10 i/o1-i/o4 v cc v ss address inputs refresh address inputs data-input/data-output row address strobe column address strobe read/write enable output enable power (+5v) ground ordering information absolute maximum ratings* symbol parameter rating unit t a t stg v in /v out v cc i out 0 ~ 70 -55 ~ 125 -1.0 ~ 7.0 -1.0 ~ 7.0 50 ambient temperature under bias storage temperature (plastic) voltage on any pin relative to v ss voltage on v cc relative to v ss short circuit output current v v ma p d 1.0 power dissipation w note: operation at or above absolute maximum ratings can adversely affect device reliability. ras cas recommended dc operating conditions (t a = 0 ~ 70c) symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 5.5 6.5 0.8 typ 5.0 - - min 4.5 2.4 -1.0 we oe c c nc no connection type no. access time package gm71c(s)17403cj/clj-5 gm71c(s)17403cj/clj-6 gm71c(s)17403cj/clj-7 50 ns 60ns 70ns 300 mil 24(26) pin plastic soj gm71c(s)17403ct/clt-5 gm71c(s)17403ct/clt-6 gm71c(s)17403ct/clt-7 300 mil 24(26) pin plastic tsop ii 50 ns 60ns 70ns
gm71c(s)17403c/cl rev 0.1 / apr ? 01 dc electrical characteristics (v cc = 5.0v+/-10%, v ss = 0v, t opr = 0 ~ 70c) symbol parameter note v oh v ol output level output "h" level voltage (i out = -2 ma ) unit max v cc 0.4 min 2.0 0 output level output "l" level voltage (i out = 2 ma ) i cc1 operating current average power supply operating current (ras, cas cycling : t rc = t rc min) i cc2 standby current (ttl) power supply standby current (ras, cas = v ih , d out = high-z) i cc3 ras only refresh current average power supply current ras only refresh mode ( t rc = t rc min) i cc4 i cc5 standby current (cmos) power supply standby current (ras, cas >= v cc - 0.2v, d out = high-z) 1 - i cc6 cas-before-ras refresh current ( t rc = t rc min) i cc7 150 - i cc8 i l(i) 10 -10 i l(o) 10 -10 input leakage current any input (0v <= v in <= 6v) output leakage current (d out is disabled, 0v <= v out <= 6 v) note: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . 4. cas = l (<=0.2) while ras = l (<=0.2). 5. l-version. edo page mode current average power supply current edo page mode ( t hpc = t hpc min) 120 - 50 ns 60 ns 70 ns 110 100 - 2 - - 100 - 50 ns 60 ns 70 ns 90 80 - - - 90 - 50 ns 60 ns 70 ns 80 70 - v v ma ua ua - standby current ras = v ih cas = v il d out = enable 5 1 ma battery backup operating current(standby with cbr refresh) (cbr refresh, t rc = 62.5us , t ras <= 0.3 us, d out = high-z, cmos interface) 350 - ua 4,5 ua 5 ma 1, 2 ma ma 2 ma 1, 3 ma 100 - 50 ns 60 ns 70 ns - - 90 80
gm71c(s)17403c/cl rev 0.1 / apr ? 01 capacitance (v cc = 5v+/-10%, t a = 25c) ac characteristics (v cc = 5v+/-10%, t a = 0 ~ 70c, notes 1, 2, 18, 19) read, write, read-modify-write and refresh cycles (common parameters) symbol parameter note c i1 c i2 c i/o input capacitance (address) input capacitance (clocks) output capacitance (data-in/out) 1 1 1, 2 unit pf pf pf max 5 7 7 min - - - test conditions input rise and fall times: 2 ns input timing reference levels: 0.8v, 2.4v output timing reference levels: 0.8v, 2.0v output load : 1 ttl gate + c l (100pf) (including scope and jig) note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable d out . symbol parameter note max unit min max min max min t rc 84 - 104 - 124 - t rp 30 - 40 - 50 - t ras 50 10,000 60 10,000 70 10,000 t cas 7 10,000 10,000 10,000 10 13 t asr 0 - - - 0 0 t rah 7 - - - 10 10 t asc 0 - - - 0 0 t cah 7 - - - 10 13 t rcd 11 37 45 52 14 14 3 t rad 9 25 30 35 12 12 4 t rsh 10 - - - 13 13 t csh 35 - - - 40 45 t crp 5 - - - 5 5 t t 2 50 50 50 2 2 7 t dzo 0 - - - 0 0 t dzc 0 - - - 0 0 gm71c(s)17403 c/cl-5 13 - - - 15 18 5 6 6 t cp 7 - 10 - 13 - random read or write cycle time ras precharge time ras pulse width cas pulse width row address set up time row address hold time column address set-up time column address hold time ras to cas delay time ras to column address delay time ras hold time cas hold time cas to ras precharge time transition time (rise and fall) oe delay time from d in cas delay time from d in oe to d in delay time cas precharge time t odd gm71c(s)17403 c/cl-6 gm71c(s)17403 c/cl-7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 22 24
gm71c(s)17403c/cl rev 0.1 / apr ? 01 read cycle symbol parameter note max unit min max min t rac - 60 - 70 t cac - 15 - 18 t aa - 30 - 35 t rcs 0 - 0 - t rch 0 - - 0 8,9,19 9,10,17,19 9,11,17,19 - 15 - 18 9 12 gm71c(s)17403 c/cl-6 t oac gm71c(s)17403 c/cl-7 t rrh 5 - - 5 12 t ral 30 - - 35 t off 15 15 13 - - t cal 18 - - 23 t clz 0 - - 0 t oez 15 15 13,23 - - t oh 3 - - 3 t oho 3 - - 3 t cdd 15 - - 18 5 t rchr t ohr t ofr t wez t wdd t rdd 60 70 3 3 15 15 15 15 18 18 - - - - - - - - - - - - access time from ras access time from cas access time from address read command setup time read command hold time to cas access time from oe read command hold time to ras column address to ras lead time output buffer turn-off time column address to cas lead time cas to output in low-z output buffer turn-off time to oe output data hold time output data hold time from oe cas to d in delay time read command hold time from ras output data hold time from ras output buffer turn off to ras output buffer turn off to we we to d in delay time ras to d in delay time max min - 50 - 13 - 25 0 - 0 - - 13 gm71c(s)17403 c/cl-5 5 - 25 - 13 - 15 - 0 - 13 - 3 - 3 - 13 - 50 3 13 13 13 - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 15 15 13,23 13
gm71c(s)17403c/cl rev 0.1 / apr ? 01 read- modify-write cycle write cycle symbol parameter max min max min t wcs 0 - 0 - t wch 10 - 13 - t wp 10 - 10 - t rwl 10 - 13 - t cwl 10 - - 13 t ds 0 - - 0 t d h 10 - - 13 write command setup time write command hold time write command pulse width write command to ras lead time write command to cas lead time data-in setup time data-in hold time gm71c(s)17403 c/cl-6 gm71c(s)17403 c/cl-7 min 0 - 7 - 7 - - - 0 - - max gm71c(s)17403 c/cl-5 7 7 7 refresh cycle symbol parameter max min max min t csr 5 - 5 - t chr 10 - 10 - t rpc 5 - 5 - gm71c(s)17403 c/cl-6 gm71c(s)17403 c/cl-7 t wrp 0 - 0 - t wrh 10 - 10 - cas setup time (cas-before-ras refresh cycle) cas hold time (cas-before-ras refresh cycle) ras precharge to cas hold time we setup time (cas-before-ras refresh cycle) we hold time (cas-before-ras refresh cycle) min 5 - 7 - 5 - gm71c(s)17403 c/cl-5 0 - 10 - max symbol parameter max min max min t rwc 136 - 161 - t rwd 79 - 92 - t cwd 34 - 40 - t awd 49 - 57 - note 15 15 14 note note 14 14 14 t oeh 15 - 18 - read-modify-write cycle time ras to we delay time cas to we delay time column address to we delay time oe hold time from we gm71c(s)17403 c/cl-6 gm71c(s)17403 c/cl-7 unit ns ns ns ns ns ns ns unit ns ns ns ns ns unit ns ns ns ns ns min 111 - 67 - 30 - 42 - 13 - max gm71c(s)17403 c/cl-5
gm71c(s)17403c/cl rev 0.1 / apr ? 01 symbol parameter note max unit min max min 25 - 30 - 35 - 40 - 9,17,19 - - 16 100,000 100,000 - - 35 40 gm71c(s)17403 c/cl-6 gm71c(s)17403 c/cl-7 edo page mode cycle 20 3 3 - - - - 9 10 13 5 5 35 40 ns ns ns ns ns ns ns ns min 20 - 30 - - - gm71c(s)17403 c/cl-5 3 - - - - 5 30 max 100,000 7 access time from cas precharge ras hold time from cas precharge edo page mode ras pulse width edo page mode cycle time output data hold time from cas low cas hold time referred oe cas to oe setup time read command hold time from cas precharge refresh symbol parameter note max unit min max min 32 - - ms refresh period refresh period (l -series) 128 - 128 - ms gm71c(s)17403 c/cl-6 gm71c(s)17403 c/cl-7 32 2048 cycles 2048 cycles edo page mode read-modify-write cycle symbol parameter note max unit min max min 68 - 79 - ns 54 - 62 - ns 14 edo page mode read-modify-write cycle time we delay time from cas precharge gm71c(s)17403 c/cl-6 gm71c(s)17403 c/cl-7 max min 57 - 45 - gm71c(s)17403 c/cl-5 max min 32 - 128 - gm71c(s)17403 c/cl-5 30 test mode cycle * 19 symbol parameter unit max note min max min 0 - 0 - ns 10 - 10 - ns gm71c(s)17403 c/cl-6 gm71c(s)17403 c/cl-7 max min 0 - 10 - gm71c(s)17403 c/cl-5 t hpc t rasp t acp t rhcp t doh t col t cop t rchp t ref t ref t hprwc t cpw t wts t wth test mode we setup time test mode we hold time
gm71c(s)17403c/cl rev 0.1 / apr ? 01 ac measurements assume t t = 2ns. an initial pause of 200us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras-only refresh or cas-before- ras refresh). if the internal refresh counter is used, a minimum of eight cas-before-ras refresh cycles are required. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . either t odd or t cdd must be satisfied. either t dzo or t dzc must be satisfied. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). assume that t rcd <= t rcd (max) and t rad <= t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. measured with a load circuit equivalent to 1 ttl loads and 100pf . assume that t rcd >= t rcd (max) and t rad <= t rad (max). assume that t rcd <= t rcd (max) and t rad >= t rad (max). either t rch or t rrh must be satisfied for a read cycles. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs >= t wcs (min), the cycles is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd >= t rwd (min), the t cwd >= t cwd (min), and t awd >= t awd (min), or t cwd >= t cwd (min), t awd >= t awd (min) and t cpw >= t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. these parameters are referenced to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. t rasp defines ras pulse width in fast page mode cycles. access time is determined by the longer of t aa or t cac or t acp notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17.
gm71c(s)17403c/cl rev 0.1 / apr ? 01 in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. after ras is reset, if t oeh >= t cwl , the i/o pin will remain open circuit (high impedance); if t oeh <= t cwl , invalid data will be out at each i/o. the 16m dram offers a 16-bit time saving parallel test mode. address ca0 and ca1 for the 4m x 4 are don't care during test mode. test mode is set by performing a we-and-cas-before- ras (wcbr) cycle. in 16-bit parallel test mode, data is written into 4 bits in parallel at each i/o (i/o1 to i/o4) and read out from each i/o. if 4 bits of each i/o are equal (all 1s or 0s), data output pin is high state during test mode read cycle, then the device has passed. if they are not equal, data output pin is a low state, then the device has failed. refresh during test mode operation can be performed by normal read cycles or by wcbr refresh cycles. to get out of test mode and enter a normal operation mode, perform either a regular cas-before-ras refresh cycle or ras-only refresh cycle. in a test mode read cycle, the value of t rac , t aa , t cac and t acp is delayed by 2ns to 5ns for the specified value. these parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. t ras (min) = t rwd (min) + t rwl (min) + t t in read - modify - write cycle. t cas (min) = t cwd (min) + t cwl (min) + t t in read - modify - write cycle. t off and t ofr are determined by the later rising edge of ras or cas. t csh (min) can be achieved when t rcd <= t csh (min) - t cas (min). 18. 19. 20. 21. 22. 23. 24.
gm71c(s)17403c/cl rev 0.1 / apr ? 01 package dimension unit: inches (mm) 24(26) tsop (type ii) 24(26) soj 0.669(17.00) max 0.661(16.80) min 0.295(7.49) min 0.329(8.38) min 0.340(8.64) max 0.147(3.75) max 0.128(3.25) min 0.020(0.50) max 0.015(0.38) min typ 0.050(1.27) 0.305(7.75) max 0.260(6.60) min 0.275(6.99) max 0.025(0.64) min 0.032(0.81) max 0.026(0.66) min 0.085(2.16) min 0.020(0.50) max 0.012(0.30) min typ 0.050(1.27) 0.007(0.18) max 0.003(0.08) min 0.047(1.20) max 0.041(1.05) max 0.037(0.95) min 0.296(7.52) min 0.303(7.72) max 0.678(17.24) max 0.670(17.04) min 0.355(9.02) min 0.371(9.42) max 0.024(0.60) max 0.016(0.40) min 0.008(0.21) max 0.004(0.12) min 0 ~ 5 o
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